8-bit CPU Simulator

Code

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; Fibonacci sequence
MOV R0, 0
MOV R1, 1
MOV R2, 10
PRINT R0
PRINT R1
MOV R3, 0
ADD R3, R0
ADD R3, R1
MOV R0, R1
MOV R1, R3
PRINT R3
SUB R2, R1
; simplified loop via JMP

Registers

R000x0000000000

R100x0000000000

R200x0000000000

R300x0000000000

R400x0000000000

R500x0000000000

R600x0000000000

R700x0000000000

ZF0

PC: 0

Output

Memory (bytes 0–31)

0000

0100

0200

0300

0400

0500

0600

0700

0800

0900

0a00

0b00

0c00

0d00

0e00

0f00

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

1a00

1b00

1c00

1d00

1e00

1f00